Capstone projects on Verilog, Jalandhar

1 3D Lifting based Discrete Wavelet Transform 2 Design of High Speed Hardware Efficient 4-Bit SFQ Multiplier 3 An Area-Efficient Universal Cryptography Processor for Smart Cards 4 A High-Speed/Low-Power Multiplier using Spurious Power Suppression Technique 5 A Lossless Data Compression Read More …

Capstone projects on Final Year, Phagwara

1. DIGITAL COMBINETION LOCK 2. SAFETY GUARD FOR THE BLIND (PROXIMITY BASE) 3. LIGHT COTROLLED DIGITAL FAN REGULATOR 4. LOW-COST ENERGY METER USING ADE 7757 5. HOME AUTOMATION AND SECURITY CONTROL INTERFACE WITH TELEPHONE 6. LINE TRACKING ROBOT/MOUSE 7. REMOT Read More …

Capstone projects on VLSI, Jalandhar

AHB and OCP Behavioral Synthesis of Asynchronous Circuits Speed Optimization of a FPGA Based Modified Viterbi Decoder Implementation of I2C Interface A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique Clamping Virtual Supply Voltage of Power Gated Circuits for Read More …

Smart city project Ludhiana Bathinda Chandigarh Patiala Jalandhar amritsar

advanced traffic lights